During the fabrication of semiconductor products, many processing steps are performed, including deposition, etching, patterning, implanting, reacting, and others, by which transistors and other electrical devices are formed and interconnected. Semiconductor manufacturers continually strive to reduce or streamline the number and duration of such processing steps, so as to increase product throughput and reduce product cost. The manufacturing processes are also optimized to improve device performance parameters and to increase device yields. In order to refine and optimize a given process flow, it is necessary to test or measure not only the electrical performance of the devices in a wafer, but also the physical properties of the structures being formed at any given point in the flow. For instance, it is often desirable to know the thicknesses of various material layers, to allow accurate adjustment of etching steps, planarization steps, or the like. In addition to optimizations, devices are often inspected to assess the continued performance of existing process flows, identify process drift, and/or the effects of material substitutions, etc.
Whereas device electrical performance in production wafers may be scrutinized to some extent using non-destructive wafer testing (e.g., prior to separation of individual device die and/or following device packaging), the physical characteristics of the structures being processed at any given point in the process flow are typically ascertained only by destructive testing of a sample wafer removed from the process. For example, where it is desired to know the extent to which a dielectric etch penetrates an etch-stop layer, a sample wafer may be removed from the process flow immediately following the etch step of interest, and sectioned for inspection using a scanning electron microscope or other metrology instrument.
The etch results may be desired to quantify etch selectivity of the process, etch rates, and/or remaining etch-stop layer thickness. Knowing the process performance, in turn, allows optimization, for instance, wherein the etch duration may be shortened according to the remaining etch-stop layer thickness. These inspections may occur, for example, in qualification of process flows prior to full scale manufacturing and/or periodically during production to verify whether process parameters are still within expected ranges. In addition to process optimization utility, the inspection of physical characteristics of a device during processing may be used to identify potential reliability problems, and to make process adjustments accordingly.
After sectioning, the exposed surface (cross-section) of the wafer is typically stained via a wet etch process, sometimes referred to as a standard oxide stain operation (SO staining). Other methods, including buffered oxide etch processing and mechanical polishing techniques, have been used in preparing the sectioned surface of interest for inspection. The sectioned surface preparation is done so as to facilitate accurate measurement of critical dimensions related to processing steps performed prior to sectioning, by delineating or differentiating the various layers of different materials from one another. The SO staining etch, for example, has been successfully employed in delineating silicon oxide (SiO2) dielectric layers from underlying silicon nitride (SiN) etch-stop layers to evaluate trench and/or via etch steps during damascene-type interconnect processing.
As device speeds continue to increase and as feature sizes and spacings continue to decrease, low-k dielectric materials are becoming more popular in forming inter layer dielectrics (ILD) in back-end interconnect processing. In addition, the dielectric constants of etch-stop layer materials are also being reduced, so as to increase operating speeds of the finished integrated circuit devices. For example, recent trends in ILD layer formation and processing include the use of carbon doped (C-doped) SiO2 for ILD layers and silicon carbide (SiC) type materials for etch-stop layers. In this case, the ILD and etch-stop layer materials are of more similar composition than were the previously popular SiO2 and SiN materials.
However, as the types of materials used in the ILD, etch-stop, hard mask, and other layers have become similar in composition, the conventional sample preparation techniques such as SO wet etch staining have become increasingly ineffective in delineating materials in different layers. Inspection of other types of layers at different points in the manufacturing flow has also suffered from the use of somewhat more similar compositions in adjacent layers in semiconductor wafers. Thus, difficulties are now arising in inspection of interconnect layers using other low-k dielectrics such as spin-on glass (SOG) films, and in other situations where adjacent layers need to be delineated. Thus, there is a need for improved sample preparation techniques by which features of interest can better be delineated for inspection in the manufacture of semiconductor devices.